1. Field of the Invention
The present invention relates to the prevention of reverse engineering of integrated circuits, and more particularly to an integrated circuit structure comprising a programmable connector/isolator between polysilicon (i.e. polycrystalline silicon) and source/drain N+ or P+ regions, to be used in a MOS-type circuit, like nMOS, pMOS or CMOS.
2. Description of the Related Art
The design, development and manufacturing efforts pertaining to semiconductor integrated circuits involve the understanding of complex structures, processes and manufacturing techniques involving smaller and smaller electronic circuitry. Efforts to be able to achieve such understanding and establish successful design, development and production manufacturing of such integrated circuits involve many man-hours of highly skilled professionals and considerable expense.
On the other hand, to avoid costly man-hours and other significant expenses some developers resort to reverse engineering practices wherein existing devices are taken apart, probed and otherwise examined to determine the physical structures of the resultant integrated circuit under review for subsequent copying. This reverse engineering, which typically relies primarily on obtaining planar optical image of the circuit, in essence attempts to by-pass typical product development efforts and expenses by studying and copying a competitive product.
Various approaches have been developed in an attempt to thwart such reverse engineering efforts, particularly in the field of semiconductor integrated circuits.
For example, U.S. Pat. No. 5,866,933 in the name of the same inventors of the present application teaches how transistors in a CMOS circuit can be connected by hidden lines between the transistors, via modifying the P+ and N+ source/drain masks. These implanted interconnections are further used to make a 3-input AND and OR circuit look substantially the same.
Moreover, U.S. Pat. No. 5,783,846 in the name of the same inventors of the present application teaches a further modification in the source/drain implant masks so that the implanted connecting lines between transistors have a gap inserted, the length of which is approximately the length of the feature size of the CMOS technology being used. If the gap is xe2x80x9cfilledxe2x80x9d with one kind of implant (depending on the implanted connecting line being p or n) the line conducts. But, if the gap is filled with the other kind of implant the line does not conduct. These gaps are called xe2x80x9cchannel blocksxe2x80x9d. Thereby the reverse engineer must determine connectivity on the basis of resolving the n or p implant at the minimum feature size of the channel block. Moreover, transistor sizes and metal connection routings are modified, to eliminate keys by which the reverse engineer can find inputs, outputs, gate lines etc. as keys to the circuit functionality.
Hence, the reverse engineer is forced to examine every transistor within the IC to determine functionality and connectivity, so that he is prevented from making effective progress. In this way, the task for the reverse engineer to discover the entire functionality of an IC containing many tens of thousands transistors is clearly impractical.
However, the modern reverse engineer has many tools to automate the viewing and analysis of the planar images of the IC. Automatic pattern recognition techniques, applied to the metal and polysilicon routing lines in the circuit, can be very effective.
The present invention prevents the above cited automatic, high level taxonomic approaches from working because the apparent routing of the signal to a transistor is broken in a way that is very difficult to detect. The protection is applied via the programming of the masks, under instruction from the circuit designer, and fits unobtrusively and cost-effectively within the standard, commercial IC process.
According to a first aspect of the present invention, an integrated circuit structure for MOS-type devices is provided, comprising: a silicon substrate of a first conductivity type; first gate insulating regions selectively placed over the silicon substrate of the first conductivity type; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulated therefrom.
According to a second aspect of the present invention, an integrated circuit structure for MOS-type devices is provided, comprising a silicon substrate of a first conductivity type, a first-level polysilicon layer, a second-level polysilicon layer and buried silicon regions of a second conductivity type buried within the silicon substrate of the first conductivity type, wherein a first set of the buried silicon regions of the second conductivity type are connected to the polysilicon layers and a second set of the buried silicon regions of the second conductivity type are isolated from the polysilicon layers to serve as fake buried contacts.
A buried contact is a known structure in integrated circuit fabrication technology, firstly developed in the late 1970""s with nMOS circuits. A buried contact provides a direct connection between polysilicon, normally the gate of a MOS transistor, and the source/drain region of a MOS transistor. To create buried contacts, contact openings are masked and etched after gate oxide growth and before deposition and patterning of polysilicon. In this way the polysilicon over the source and/or drain regions can make direct contact to the source and/or drain regions by means of the buried contact openings.
The present invention discloses an integrated circuit structure and a process for preventing reverse engineering of integrated circuits, by use of a buried contact process that provides the opportunity for a programmable connector/isolator. In particular, the buried contact process employs at least two polysilicon layers. Such is the case in virtually all CMOS processes that manufacture DRAMs and EEPROMs. The process according to the present invention will make it possible to selectively interrupt the apparent conduction connections at various transistors sources and drains throughout the circuit.
Polysilicon has long been used to form the gates for MOS transistors, see for example VLSI technology, S. M. Sze, McGraw-Hill, 1983 p. 99. This requires a CMOS process having one level of deposited polysilicon. CMOS processes employing two polysilicon layers, the two layers typically being separated by an oxide layer, make possible the formation of capacitors and electrically eraseable read only memories (EEPROMs), see Hodges and Jackson, Analysis and Design of Digital Integrated Circuits, 2d. ed., McGraw-Hill, 1988, p. 353. See also S. M. Sze, supra, pp. 461-465, for a reference to buried contact devices. The concept of the buried contact using two levels of polysilicon is preferably being considered for processes having minimum feature sizes approaching or below 0.2 xcexcm.
According to the present invention, the buried contact can be placed in correspondence of a first or a second level of polysilicon placed thereover, and in this way be programmed to be a connection or isolation. In particular, when the buried contact is placed under the first level of polysilicon, it acts as a connection. On the contrary, when the buried contact is placed under the second level of polysilicon, it acts as an isolation. In this last case, a thin gate oxide under the second level polysilicon is provided, in order to insulate the second level polysilicon from the buried contact. Therefore, the circuit designer can xe2x80x9cprogramxe2x80x9d the use of the buried contact according to different schemes, by provision of a dual deposition of the thin gate oxide, as later explained in detail.
In an integrated circuit realized according to the present invention, a reverse engineer will find it very difficult to determine the presence of a thin gate oxide between the polysilicon and the source and/or drain region of a nMOS device, a pMOS device or a CMOS device.